CS42448-Verilog-Example

CS42448 FPGA Verilog Loop Back Example

This is a basic Verilog CS42448 ADC -> DAC Channel 0 forwarding.

Plug a input signal from signal generator and measure the output of the CH0 via oscilloscope.

Board Design can be referenced to CS42448 Evaluation Board.

Clock of the board is set to 12.288MHz and source is 100MHz.

The resource are low (Spartan 7 implementation):