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Cyclone-V-MIPI-OV13850

Cyclone-V-MIPI-OV13850

Cyclone V SoC MIPI CSI-2 OV13850

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paypal.me/briansune

Quartus Project Resource

+-----------------------------------------------------------------------------------+
; Flow Summary                                                                      ;
+---------------------------------+-------------------------------------------------+
; Revision Name                   ; ddr512_base                                     ;
; Top-level Entity Name           ; top                                             ;
; Family                          ; Cyclone V                                       ;
; Device                          ; 5CSEBA5U19C6                                    ;
; Timing Models                   ; Final                                           ;
; Logic utilization (in ALMs)     ; 2,331 / 32,070 ( 7 % )                          ;
; Total registers                 ; 5065                                            ;
; Total pins                      ; 174 / 205 ( 85 % )                              ;
; Total virtual pins              ; 0                                               ;
; Total block memory bits         ; 1,562,624 / 4,065,280 ( 38 % )                  ;
; Total DSP Blocks                ; 0 / 87 ( 0 % )                                  ;
; Total HSSI RX PCSs              ; 0                                               ;
; Total HSSI PMA RX Deserializers ; 0                                               ;
; Total HSSI TX PCSs              ; 0                                               ;
; Total HSSI PMA TX Serializers   ; 0                                               ;
; Total PLLs                      ; 6 / 6 ( 100 % )                                 ;
; Total DLLs                      ; 1 / 4 ( 25 % )                                  ;
+---------------------------------+-------------------------------------------------+

Hardware

HW no Description Image
1 CMOS (camera)
2 Development Board

Feature and Support

1) LW-H2F register controlled R-G-B gain. 2) Simple CMOS debayer 3) Loop-back to HDMI via FPGA2SDRAM 4) I2C control and adjust via HPS2FPGA fabric. 5) Reset\Power control pin via HPS to FPGA fabric IO. 6) ToDo VCM auto focus control via IIC.

CMOS Capture image

VCM Auto Focus Control CAM1302 - DW9718 (Success)

To control the VCM, user must power on via reg 0x00.

Then setup the below registers settings.

For 10-bit DAC registers are 0x02, 0x03.

DAC 10bit <- Near focus higher value, far focus low value.

Simple i2c control

$ sudo i2cget -y 3 0x0c 0x01
0x0c
$ sudo i2cget -y 3 0x0c 0x02
0x01
$ sudo i2cget -y 3 0x0c 0x03
0x90
$ sudo i2cget -y 3 0x0c 0x04
0x33
$ sudo i2cget -y 3 0x0c 0x05
0x60
$ sudo i2cget -y 3 0x0c 0x10
0x00

ToDo

Contact

briansune@gmail.com