Delta-Sigma-DAC-Verilog

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The measurements are conducted on Spartan 7 Xilinx FPGA with LPF setting - (680R, 1nF).

Common questions:

Why it work?

1 bit flip-flop the basic building block of a R-2R DAC hences it is a DAC because it can convert logic to voltage.

Of cause it is just limited to 0 - low voltage, 1 - high voltage.

When it is modulated with a carrier frequency it start to make all senses that it can be a really good DAC.

Why two stages?

The best answer can be referenced from : https://www.beis.de/Elektronik/DeltaSigma/1stOrderDisadvantages.html https://www.youtube.com/embed/4SIJTl5du60?start=1300

In short when 0 or max (-ve, +ve) is insert to the DAC, the output will result in high tone amputitude that can be reduce via 2 stages.

Oscillscope Measure:

Single Stage Delta-Sigma DAC:

Resource on FPGA:

What bitwidth is required on the first stage?

This is commonly considered with i.e. 16bit Input + 2bit.

Two Stage Delta-Sigma DAC:

Resource on FPGA:

There are a major question when designing the ΔΣ DAC:

What bitwidth is required on the second stage?

My approach is considering 1st stage output i.e. [16bit + 2bit] + over_sample_rate (i.e. 2^[6] 6bit).

over_sample_rate for example 2^6 or above