Kintex 7 MIPI DSI 10.1” LCD

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More MIPI DSI LCD examples

Please visit FPGA-TFT-MIPI-or-DPI or FPGA-LCD-MIPI-or-DPI

Background

In the past, many Xilinx FPGA developers and users wanted to utilize the “MIPI DSI TX Controller Subsystem” IP.

Unfortunately, due to the absence of LPDT, users were unable to initialize the LCD/TFT display. Hence, the usefulness of this built-in Vivado IP was highly limited.

In this project, a novel, ultra-low-resource, Verilog-based HDL design has been developed to address this niche need.

This design requires neither a softcore nor a hardcore (using only pure FSM + LUT), significantly reducing complexity.

Additionally, the design is independent of Vivado IP (excluding inherent FPGA building blocks) and does not require a DPHY IP either.

Demonstration

Test Patterns

BPP,FPS,FPGA,Lanes,I/F	Video
16, 60,K7,4,R-Net
24, 60,K7,4,R-Net

Experiment findings

According to Xilinx and Intel document, users are required to control the length between FPGA differential I/O to LCD/TFT I/F must kept as short as possible.
However, in this 10.1" LCD experiment, it is not necessary to maintain a short cable length.
Trade-off can be made between length of the cable and MIPI-DSI clock frequency, which this LCD is using a long cable (200 mm) @clock freq. 500Mbps.

How to obtain the design?

Please contact via EMAIL: briansune@gmail.com

How to Use?

1) Modify the Python script and convert the initialization LPDT ROM (read-only-memory) 2) Make sure the hardware is MIPI DSI supported. Xilinx FPGA please check HERE or Altera FPGA please check HERE 3) Make sure the MMCM and parameters are converged 4) Ensure the MIPI Mbps is lower than 900, which is tested on the 5.5 inch 1080p TFT 60 FPS.

Hardware

Description	EVM
FPGA K7-R-Net
10.1” LCD

Project Resource

BPP,FPS,FPGA,Lanes	Resources
16,60,K7,4
24,60,K7,4

Project Heirachy

Remarks 1: Ultrascale+ devices and 7 series have different serialization building blocks.

Remarks 2: Ultrascale+ devices have MIPI physical interface, which no extra resistor-network or front-end ICs are needed.

Remarks 3: The only Verilog design that are changed to cope with Ultrascale+ device are the serialization and MMCM blocks.

 |-mipi_init_script
 | |-main.py
 | |-mipi_setup_rom.mem
 | |-one_lane_lcd.txt
 |-mipi_phys
 | |-mipi_crc.v
 | |-mipi_ecc.v
 | |-mipi_hs_clk_phy.v
 | |-mipi_hs_phy.v
 | |-mipi_lps_phy.v
 |-mipi_refclks
 | |-mipi_refclks.v
 |-mipi_setup
 | |-mipi_lpdt_setup.v
 | |-mipi_reset.v
 | |-mipi_setup_rom.mem
 |-mipi_sim
 | |-tb_mipi_setup.v
 | |-tb_mipi_top.v
 | |-tb_mipi_video.v
 |-mipi_top.v
 |-top.xdc
 |-video_src
 | |-mipi_long_vid_pack.v
 | |-mipi_remap.v
 | |-mipi_short_vid_hdr.v
 | |-mipi_video_stream.v
 | |-test_pattern_gen.v
 | |-video_timing_ctrl.v