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Spartan-6-MIPI-DSI-5.5-inch-LCD

Spartan-6-MIPI-DSI-5.5-inch-LCD

Spartan 6 MIPI DSI 5.5” LCD

If this project is constructive, welcome to donate a drink to PayPal.

or

paypal.me/briansune

More MIPI DSI LCD examples

Please visit FPGA-LCD-MIPI-or-DPI or FPGA-TFT-MIPI-or-DPI

Background

In the past, many Xilinx FPGA developers and users wanted to utilize the “MIPI DSI TX Controller Subsystem” IP.

Unfortunately, due to the absence of LPDT, users were unable to initialize the LCD/TFT display. Hence, the usefulness of this built-in ISE IP was highly limited.

In this project, a novel, ultra-low-resource, Verilog-based HDL design has been developed to address this niche need.

This design requires neither a softcore nor a hardcore (using only pure FSM + LUT), significantly reducing complexity.

Additionally, the design is independent of ISE IP (excluding inherent FPGA building blocks, FIFO & BROM) and does not require a DPHY IP either.

Demonstration

Test Patterns

BPP,FPS,FPGA,Lanes,I/F Video
16, 60,K7,4,R-Net 16 BPP 50FPS
24, 60,K7,4,R-Net 24 BPP 50FPS

How to obtain the design?

Please contact via EMAIL: briansune@gmail.com

How to Use?

1) Modify the Python script and convert the initialization LPDT ROM (read-only-memory) 2) Make sure the hardware is MIPI DSI supported. Xilinx FPGA please check HERE or Altera FPGA please check HERE 3) Make sure the MMCM and parameters are converged 4) Ensure the MIPI Mbps is lower than 900, which is tested on the 5.5 inch 1080p TFT 60 FPS.

Hardware

Description EVM
FPGA S6-R-Net
FPGA S6-Board
FPGA S6-IF
5.5” LCD

Project Resource

16bpp 4 Lanes 50fps

Slice Logic Utilization:
  Number of Slice Registers:                   877 out of  30,064    2%
  Number of Slice LUTs:                      1,127 out of  15,032    7%
  Number of occupied Slices:                   410 out of   3,758   10%
  Number of MUXCYs used:                       356 out of   7,516    4%
  Number of LUT Flip Flop pairs used:        1,247
    Number of fully used LUT-FF pairs:         617 out of   1,247   49%
    Number of unique control sets:              78
IO Utilization:
  Number of bonded IOBs:                        23 out of     186   12%
    Number of LOCed IOBs:                       18 out of      23   78%
Specific Feature Utilization:
  Number of RAMB16BWERs:                         7 out of      52   13%
  Number of RAMB8BWERs:                          0 out of     104    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             2 out of      32    6%
  Number of BUFG/BUFGMUXs:                       6 out of      16   37%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     272    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     272    0%
  Number of OLOGIC2/OSERDES2s:                  10 out of     272    3%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     160    0%
  Number of BUFPLLs:                             2 out of       8   25%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      38    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            2 out of       2  100%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

24bpp 4 Lanes 50fps

Slice Logic Utilization:
  Number of Slice Registers:                 1,030 out of  30,064    3%
  Number of Slice LUTs:                      1,404 out of  15,032    9%
  Number of occupied Slices:                   452 out of   3,758   12%
  Number of MUXCYs used:                       420 out of   7,516    5%
  Number of LUT Flip Flop pairs used:        1,514
    Number of fully used LUT-FF pairs:         730 out of   1,514   48%
    Number of unique control sets:              91
IO Utilization:
  Number of bonded IOBs:                        23 out of     186   12%
    Number of LOCed IOBs:                       18 out of      23   78%
Specific Feature Utilization:
  Number of RAMB16BWERs:                         8 out of      52   15%
  Number of RAMB8BWERs:                          0 out of     104    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 2 out of      32    6%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             2 out of      32    6%
  Number of BUFG/BUFGMUXs:                       6 out of      16   37%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     272    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     272    0%
  Number of OLOGIC2/OSERDES2s:                  10 out of     272    3%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     160    0%
  Number of BUFPLLs:                             2 out of       8   25%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      38    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            2 out of       2  100%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Project Hierarchy

Remarks 1: Ultrascale+ devices and 7 series have different serialization building blocks.

Remarks 2: Ultrascale+ devices have MIPI physical interface, which no extra resistor-network or front-end ICs are needed.

Remarks 3: The only Verilog design that are changed to cope with Ultrascale+ device are the serialization and MMCM blocks.

 |-clog2.vh
 |-mipi_init_script
 | |-four_lanes_lcd_init.txt
 | |-main.py
 | |-mem_to_coe.py
 | |-mipi_setup_rom.coe
 | |-mipi_setup_rom.mem
 |-mipi_parameters.vh
 |-mipi_phys
 | |-mipi_crc.v
 | |-mipi_ecc.v
 | |-mipi_hs_clk_phy.v
 | |-mipi_hs_phy.v
 | |-mipi_lps_phy.v
 |-mipi_refclks
 | |-mipi_refclks.v
 |-mipi_setup
 | |-mipi_lpdt_setup.v
 | |-mipi_reset.v
 | |-mipi_setup_rom.coe
 |-mipi_sim
 | |-ise_sim_vid.wcfg
 | |-tb_mipi_setup.v
 | |-tb_mipi_top.v
 | |-tb_mipi_video.v
 |-mipi_top.ucf
 |-mipi_top.v
 |-test_mipi.tcl
 |-video_src
 | |-mipi_long_vid_pack.v
 | |-mipi_remap.v
 | |-mipi_short_vid_hdr.v
 | |-mipi_video_stream.v
 | |-test_pattern_gen.v
 | |-video_timing_ctrl.v
 |-xpm2ise_macro
 | |-xpm_cdc_array_single.v
 | |-xpm_cdc_single.v
 | |-xpm_memory_sprom.v